Our project was to design a Reduced Instruction Set Computer (RISC) using a specialized hardware description language, and to implement the design on an Erasable Programmable Logic Device (EPLD).
The project had some specific design specifications that had to be met but the rest of the design was left up to us. The design specifications that had to be met were that:
1. Processor would be a true 32-bit processor. That is, both the instruction size and the datapath would be 32-bits.
2. Processor would follow a Von Neuman style architecture. That is, have a single memory, rather than have separate memories for instruction and data.
3. In a register style instruction there would be one write register and two read registers.
ARM Processor
ARM Processor
ARM Processor
ARM Processor
ARM Processor
ARM Processor
ARM Processor
ARM Processor
Microsoft shows off ARM processors running Windows
HC23-K1: ARM Processor Evolution
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